CS 354 Computer Organization and Systems Fall 2017 

Project 6 - Memory Circuits


In this project you will work with Logisim to create a functioning bank of 4 1-bit memory cells using D latches.


Computers need to store information internally for a varitey of purposes. One important place memory cells are used is in the register file.


Simulated S-R Latch: Implement a S-R Latch in Logisim. Clearly label the inputs and outputs in your Logisim drawing. Verify it has the functionality we discussed in class.

Simulated D Latch: Using your copies of S-R latch, implement a D Latch in Logisim. The D Latch has 2 inputs: a data line and a clock signal. The memory is set when the clock is 1 and will hold that state after the clock line goes to zero.

Memory Bank: Using you copies of D-Latch, implement a bank of four D latches. For testing, you can connect the output of each D latch to an LED. You can think of these as locations 00, 01, 10, and 11.

Controlling the Memory Bank: Provide two line that specify the address that will either be read or written. Provide one output line for data input, one line for data output, and one line for a write signnal.

Reading from the Memory Bank: Use a multiplexor with 2 control lines, so that one of four inputs can be selected. The selected D latch will send its output through the multiplexor to the output line. The input line is ignored.

Writing to the Memory Bank: The data line is connected to the data input of each D Latch. To write the value into the specified location, the associated clock signal needs to be 1. When the clock line is asserted, the data line value will be written to the D latch indicated by the address bits. You will write to the appropriate D latch when decoder line matches AND the write signal is asserted. Use a decoder to control which D latch to read, requiring 2 address bits. Recall that a decoder with two control lines will have four outputs with exactly one having the value 1.


Send me an email of your Logisim circuit file (.circ) for the 1-bit ALU (using the NAND full adder) as an email attachment. Also submit a hardcopy of your Logisim circuit.


  1. Appendix C

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