CS 354 Computer Organization and Systems Fall 2017 

Project 5 - Arithmetic Logic Unit (ALU) Circuitry


In this project you will create a functioning 4-bit Arithmetic Logic Unit using logisim.

Arithmetic Logic Unit

At the very heart of computers is their ability to compute logical operations that can be interpreted as arithmetic computations. The part of the computer that performs these operations is called the Arithmetic Logic Unit or just simply the ALU. This is described in section C.5 in Appendix C of your text.

Let's think abstractly about the ALU for now. The figure above shows a 1-bit ALU as described in your text. Ignore the internal components and focus on the interface (inputs and outputs). The ALU has several inputs:

  • Data Inputs
    • A is the first data input value
    • B is the other data input value
    • Carry_In provides the Carry from addition in the previous place value
    • Less provide a less than signal for an aggregate collection of ALUs
  • Control Signals
    • A_Invert drives a multiplexor to optionally invert the value of A
    • B_Invert drives a multiplexor to optionally invert the value of B
    • Operation (2 bits: Op_0 and Op_1)
The ALU also has two outputs:
  • Result is the output of the computation performed by the ALU
  • Carry_Out is the carry to send to the next place value
Often it is instructive to think of the ALU as simply a box that has some inputs and outputs and performs the specified function. In some ways, when we look at an integrated circuit, all that is typically visible is the connections of the housing. The complex circuitry on the chip is completely hidden from the the outside world and all one sees is the interface.

While it is often useful to think of the CPU as a black box, the goal of this course is for you to see all the gory details! Let's actually see how an ALU performs the computations and why they are correct. Underneath the interface layer, the main components of the ALU are:

  • A full adder that takes two bits plus a carry and produces a sum and carry (recall you did this in Project 1)
  • An AND gate for ANDing the input values together
  • An OR gate for ORing the input values together
  • Inverters for NOTting the values of A or B
The operation of the ALU is controlled by three multiplexors (MUXes). The two MUXes associated with inverting A and B select one of two inputs based on the value of the associated control line (A_Invert and B_Invert). The third MUX selects one of four possible ALU operations based on two input bits (Op_0 and Op_1).

Recall that a MUX allows the selection of one of 2n data inputs from n control inputs. The figure below shows how a MUX can be constructed using NOT and AND gates. Note the pattern of inputs to the AND gates follows the pattern seen in the binary representation of the integers from 0 to 3 (010=002, 110=012, 210=102, 310=112). With this knowledge you should be able to create and understand a MUX of any size.


1-bit ALU: Implement the 1-bit ALU shown in the figure above in Logisim.

Simple 4-bit ALU: Implement a 4-bit ALU using 4 copies of your 1-bit alu, similar to the 32-bit version from Figure C.5.7. You can use a hex display from logisim for your inputs and outputs. Unfortunately you will need to provide four single bit inputs for both A and B.

Advanced 4-bit ALU: Implement a 4-bit ALU using 4 copies of your 1-bit alu, similar to the 32-bit version from Figure B.5.12 (or the electronic C.5.12). This version connects the set output (adder output) from alu3 to the input on alu0. Also, implement the overflow detection circuitry to allow detection of overflow. The overflow is always generated, but only valid if the operation is add. See Figure 3.2 in your text (page 180) for when an overflow is present. Start by creating a truth table for your overflow conditions; it will have 6 inputs, but only 4 combinations where there is overflow. Convert your truth table into a circuit.


Send me an email of your Logisim circuit file (.circ) for the 4-bit ALU an email attachment. Don't include extraneous circuitry in your final submission.


  1. Appendix B (electronic C)

Copyright © 2017, David A. Reimann. All rights reserved.